ESim/C4/Mixed-Signal-Simulation-using-NgVeri/English

In this tutorial, we have

• Opened and edited a file in Makerchip
• Created an Ngspice model using NgVeri and
• Generated plots using an Ngspice model

Visual cue	Narration
Show Slide: Title slide	Welcome to the Spoken Tutorial on Mixed Signal Simulation using NgVeri.
Show Slide: Learning Objectives	In this tutorial, we will learn to Open and edit a file in Makerchip Create an Ngspice model using NgVeri and Generate plots using an Ngspice model.
Show Slide: System Requirements	To record this tutorial, I am using Ubuntu Operating System version 20.04 eSim v2.2 The process demonstrated in this tutorial is similar in Windows OS also.
Show Slide: Pre-requisites https://spoken-tutorial.org	To follow this tutorial, The learner must have basic knowledge of eSim. For pre-requisite eSim tutorials, please visit this website.
Show Slide: Code Files	The files used in this tutorial are provided in the Code files link. Please download and extract the files. Make a copy and then use them while practicing.
Only Narration	Let us look at the features of Makerchip and NgVeri.
Slide: Features of Makerchip-NgVeri	The Makerchip interfaces the online Makerchip IDE with eSim. The NgVeri converts a Verilog code file to its respective NgVeri digital model. The created models are used for mixed signal circuit simulation in eSim.
eSim main window: Switch to the eSim window	Now, let us learn about the Makerchip-NgVeri feature in eSim. I have already opened eSim.
Click on the Makerchip-NgVeri icon	Click on the Makerchip-NgVeri icon from the left toolbar.
Makerchip-NgVeri Tab: Point to the Makerchip tab	In the right panel, we can see two tabs. The first tab is the Makerchip. It is used to open and edit a Verilog file and launch the Makerchip IDE.
Show Slide: Supported File formats	Let us look at the file formats that can be opened in the Makerchip tab. The supported file formats are: .tlv which is a Transaction-Level Verilog .v stands for the Verilog and .sv stands for System Verilog
Makerchip-NgVeri Tab: Point to the NgVeri tab	The second tab is the NgVeri tab. It is used to run the Verilog to Ngspice converter.
Makerchip-NgVeri tab: Click on the Makerchip tab	I will click on the Makerchip tab. Let us see how to open a verilog file in the Makerchip tab.
Click on Add Top Level Verilog file	Click on the Add Top Level Verilog file option.
Point towards Open Verilog Directory dialog box	The Open Verilog Directory window opens. I have already downloaded the counter4bit.v file from the codefile link.
Select counter4bit.v file Click on Open Highlight the code according to narration	Locate and select the verilog file counter4bit.v from the Downloads folder. Then click on Open button on the top right corner. We see that the file is opened on the .tlv file window. This verilog code contains two one bit inputs as clock and reset. The counter output counts up at the positive edge of the clock input. The counter output resets to 0000 when it reaches 1111. It also resets when the reset input is held high.
Point to Path to .tlv file	The Path to the .tlv file is displayed above the .tlv code window. Note that there should not be any spaces or special characters in the filepath as shown here.
Only narration	Now, let us see how to Edit and Save the verilog code. First, I will edit the file by adding a comment. The comment needs to be added at the beginning of the .tlv code file.
Type //This is a counter example	Similar to C language, a comment is added after a double slash. So, I will type double slash This is a counter example in the .tlv window.
Click on Save	Click on the Save option under the Makerchip tab.
Click on OK	Then, click on the OK button in the confirmation dialog box.
Click on the Refresh option	We observe that the Refresh option is blinking since the file is not saved. So, let us click on the Refresh option. The modifications made in the file are now saved.
Point to the Refresh option	The Refresh option blinks whenever the file is edited and not saved.
Only Narration	We will learn about the other options in the Makerchip tab in the future tutorials.
Only Narration	Let us now look at the options available in the NgVeri tab.
Click on the NgVeri tab	Click on the NgVeri tab.
Point to the Run Verilog to NgSpice Converter option	The first option is the Run Verilog to NgSpice Converter. It converts a verilog file into an Ngspice model.
Makerchip-NgVeri Tab: Click on the Run Verilog to NgSpice converter option	Now let us click on the Run Verilog to NgSpice Converter. The previously opened counter4bit.v Verilog file will now be converted into an Ngspice model.
Point to the Warning dialog box	After clicking, a Warning dialog box pops up.
Click on OK	To update the changes, click on the OK button.
Makerchip-NgVeri Tab: Highlight the message Running NgVeri	Scroll up in the Terminal window. We see the message Running NgVeri is getting displayed.
Highlight Model created successfully	The process may take some time to complete. On completion, we see Model created successfully in the Terminal in green color.
Scroll Up the Terminal	Let us scroll up and look at each command that was executed in the Terminal.
Highlight RUN VERILATOR	The first command is RUN VERILATOR.
Highlight MAKE VERILATOR	Then, scroll down to see the next command. The second command is MAKE VERILATOR.
Highlight COPYING FILES	Then the third command is COPYING FILES.
Highlight MAKE COMMAND	The fourth command is the MAKE command to compile an Ngspice.
Highlight MAKE INSTALL COMMAND	Next, the fifth command is MAKE INSTALL command to install the changes in Ngspice.
Only narration	If you are using a .tlv code, you will see an additional command as RUN SANDPIPER-SAAS.
Highlight Model created successfully	The commands in the Terminal ensure that NgVeri is running successfully.In case of any error, the commands will be highlighted in red color. The model has been generated.
Click on Clear Terminal	Click on the Clear Terminal option to clear the terminal.
Only narration	Now, let us see an example of a mixed signal project on the counter. I have already downloaded the counter folder from the Code File link.
Click on the Open Project icon on the top left toolbar	Let us generate the schematic representation of the counter circuit. For that, let us load the counter folder on the left panel. Click on the Open Project icon on the eSim top left toolbar.
Double-click on the Downloads folder Click on the counter folder	Now, locate the Downloads folder and click on it. Then select the counter folder.
Click on the OK button at the top	Click on the Open button at the top. Now the counter project appears under the Projects on the left panel.
eSim main window: Click on counter project Click on Open Schematic	Let us now open the schematic. To do so, I will select the counter project from the left side Projects panel. Then click on the Open Schematic icon on the left toolbar.
Point to counter4bit block	The counter4bit block represents the digital model created using NgVeri.
Point to the adc_bridge_2	The ADC bridge is an interface between the input analog and digital blocks.
Point to the dac_bridge_4	The DAC bridge is an interface between the digital and output analog blocks.
Only Narration	I have generated a netlist and annotated the schematic. Please pause the tutorial and do the same. For any clarifications, please refer to the previous tutorials.
Close schematic window	Let us now close the schematic window and return to the eSim main window.
Click on Convert KiCad to Ngspice converter icon	Click on the Convert KiCad to Ngspice icon from the left toolbar.
Click on the Ngspice Model tab	Let us set the simulation parameters of bridges. In the right panel, under kicadToNgspice-2 window, click on Ngspice Model tab.
Click on in_low and type 0.5 Click on in_high and type 3.3	Let us add the ADC parameters. in_low represents the Minimum Input Low Voltage. Let us set in_low as 0.5. in_high represents the Maximum Input High Voltage. Let us set in_high as 3.3.
Click on out_low and type 1 Click on out_high and type 3.3	Let us add the DAC parameters. out_low represents the Minimum Output Low Voltage. Let us set out_low to 1. out_high represents the Maximum Output High Voltage. Let us set out_high as 3.3. Default values are considered if the user does not fill the remaining parameters.
Only Narration	In order to set parameters in other tabs, please refer to the previous eSim tutorials.
Click on the Convert option	Then click on the Convert option at the bottom.
Click on OK	Finally, click on the OK button in the confirmation dialog box. A new netlist gets created with the simulation parameters.
eSim main window: Click on the Simulation icon	Let us now simulate the circuit. To do so, click on the Simulation icon from the left toolbar.
Only Narration	Ngspice begins to run in order to simulate the circuits. We see that output has been generated in different windows.
Point to all the plots	The counter output plots are o0, o1, o2 and o3. The plots change at the positive edge of the clock.
Point to the plot o0	o0 is the LSB of the output.
Point to the plot o1	o1 is the second bit of the output.
Point to the plot o2	o2 is the third bit of the output.
Point to the plot o3	o3 is the MSB of the output.
Point to the counter.cir.out Window	In the counter.cir.out Window, we see the values of the counter ports. Hereby, we have completed simulating a mixed signal circuit using NgVeri .
Show Slide:Summary	This brings us to the end of this tutorial. Let us summarize.
Show Slide: Assignment	As an assignment, please do the following: Open the file shift.v in Makerchip - NgVeri shift.v file is available in codefile link Run Verilog to NgSpice Converter If Model created successfully, create a new project Create a new schematic using the shift block Generate Netlist and run KiCad to Ngspice Converter Add simulation parameters and run the simulation Verify the input and output plots
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Show Slide: Acknowledgement	The Spoken Tutorial project is funded by the Ministry of Education, Government of India.
Show Slide: Thank you	This is Josiga, a FOSSEE summer fellow 2022, IIT Bombay signing off. Thanks for joining.

Contributors and Content Editors

Nancyvarkey, Nirmala Venkat