Difference between revisions of "ESim/C4/Mixed-Signal-Simulation-using-NGHDL/English"
| Line 439: | Line 439: | ||
* Locate the '''counter '''folder which is available in this path. | * Locate the '''counter '''folder which is available in this path. | ||
| − | + | '''eSim-2.2/nghdl/Example/combinational-logic'''. | |
| − | '''eSim-2.2/nghdl/Example/combinational-logic'''.* Upload the '''up_counter.vhdl '''file on the '''Ngspice Digital Model Creator'''. | + | * Upload the '''up_counter.vhdl '''file on the '''Ngspice Digital Model Creator'''. |
* Create a''' schematic''' representation of the''' up_counter ''' | * Create a''' schematic''' representation of the''' up_counter ''' | ||
* Annotate the '''schematic'''. | * Annotate the '''schematic'''. | ||
Revision as of 15:42, 5 January 2023
| Visual Cue | Narration |
| Slide: Title | Welcome to the spoken tutorial on “Mixed Signal Simulation using NGHDL”. |
| Show Slide:
Learning Objectives |
In this tutorial, we will learn
|
| Show Slide:
System requirements |
To record this tutorial, I am using
The process demonstrated in this tutorial is similar in Windows OS also. |
| Show Slide:
Pre-requisites |
To follow this tutorial,
|
| Show Slide:
Code Files |
|
| Show Slide:
What is Mixed Signal Simulation? |
The mixed signal simulation is the simulation of mixed signal circuits.
It is a combination of,
|
| Show Slide:
What is NGHDL? |
The NGHDL feature converts a VHDL code file to its respective NGHDL digital model.
The created models are used for mixed signal circuit simulation in eSim. |
| Show Slide:
File Type |
To create an NGHDL digital model, the input file should be in .vhdl format.
VHDL is a Hardware Description Language to model digital circuits. |
| Open eSim | Let us now explore the NGHDL option.
I have already opened the eSim software on my desktop. |
| Click on the NGHDL icon in the left toolbar in eSim | Then navigate to the left toolbar and click on the NGHDL icon.
The Ngspice Digital Model Creator window opens. |
| Cursor on Browse, Add files and Remove files buttons
Cursor on the Upload button at the bottom. |
It has 3 buttons at the top right corner. These buttons are used to, * Browse
It has an Upload button at the bottom. It uploads and converts the added VHDL file into an NGHDL digital model. |
| Point to the submodules window | The white window on the upper part is the submodules window.
It shows all the files that have been added. |
| Point to the terminal window | The black window on the lower part is the terminal.
It displays all the build commands while running NGHDL. |
| Click on the Browse button on the Ngspice Digital Model Creator window | Let us create an NGHDL digital model of a full_adder by uploading its VHDL file.
The first step is to add the .vhdl file. To add the required file, I will click on the Browse button. An Open File window opens. |
|
Click on the eSim-2.2 folder Click on the nghdl folder Click on the Example folder Click on the combinational_logic folder Click on the full_adder folder |
Let us open the full_adder VHDL example file which is available in eSim.
Click on the eSim-2.2 folder. Then click on the nghdl folder. In that, click on the Example folder. Next, click on the combinational_logic folder. Finally, click on the full_adder folder. |
| Click on full_adder_sl.vhdl file
Click on the Open button Hover cursor over the Textbox |
Select the full_adder_sl.vhdl file.
Now, click the Open button at the top. We see the path of the file is displayed in a textbox at the top. The full_adder_sl.vhdl file contains the VHDL code for the full_adder model. The code adds three binary inputs, to give sum and carry output. |
| Only narration | For some program, the dependency files may needed to be added or removed.
So, let us learn how to add and remove the dependency files. For demonstration purposes, I will use the .vhdl file of half_adder. |
| Click on the Add Files button
Click on the combinational_logic folder Double-click on the half_adder folder. |
To do so, first, click on the Add Files button to add the dependency file.
Now, go back to the combinational_logic folder. Then, click on the half_adder folder. |
| Click on half_adder.vhdl file
Click on the Open button |
We see the half_adder.vhdl file. Click on it.
To open the file, click on the Open button at the top. |
| Point to the submodules window | We see the path of half_adder.vhdlis displayed in the submodules window.
Likewise, we can add as many files as required as dependencies. |
| Click on Remove Files Button | Now, let us see how to remove the added half_adder.vhdl.
First, click on the Remove Files button. |
| On nghdl dialog box | nghdl dialog box opens which shows the earlier added files. |
| On the nghdl dialog box,
Click on the checkbox and then click on the Remove Button |
Click on the check box and then click on the Remove button.
The half_adder.vhdl file is now removed. In a similar way, the redundant files can be removed. |
| Click on the Upload button | The next step in creating the NGHDL digital model is uploading the VHDL file.
So I will click on the Upload button at the bottom. Now it will generate the full_adder_sl NGHDL digital model. |
| Click OK on the Library added dialogue box | After it is completed, a dialog box opens.
It shows that a library is added to KiCad. Which means that the NGHDL digital model has been created. Click on OK to close it. |
| Scroll and point to the NGHDL terminal window | We see the build commands in the NGHDL terminal window.
Error messages will be shown on the terminal if there are any. As of now, we do not see an error in the terminal window. So, we confirm that NGHDL has created the model of full_adder_sl successfully. |
| Click on the Exit button in the Ngspice Digital Model Creator window | To close the window, click on the Exit button at the bottom. |
| Only narration | Now, let us see an example of a mixed signal project on full_adder.
I have already downloaded the project files from the Code File link |
| Click on the Open Project button on the top toolbar | Let us generate the schematic representation of the full_adder circuit.
For that, let us load the full_adder folder on the left panel. Click on the Open Project button on the eSim top toolbar. |
| Double-click on the Downloads folder
Click on the full_adder folder |
Now, locate the Downloads folder and select the full_adder folder. |
| Click on the Open button | Click on the Open button at the top.
Now the full_adder project appears under the Projects on the left panel. |
| Double click on the full_adder project in the Projects Panel | Double-click on it to select and see the files inside the full_adder folder. |
| Click on the Open Schematic icon | Next, click on the Open Schematic icon on the left toolbar.Please note that the project path should not contain a space. |
| Point to analog and digital parts. | We see the schematic of the full_adder is opened.
The circuit consists of both analog and digital parts. |
| Point to pulse sources and plots. | The pulse sources and plots are the analog blocks. |
| Point to full_adder_sl block. | The full_adder_sl is the digital block generated from the VHDL code.
It accepts and sends only digital signals. |
| Point to adc_bridge_3 | The ADC bridge converts the pulse sources to digital signals.
It acts as the input for the full_adder_sl block. |
| Point to dac_bridge_2 | The DAC bridge converts the digital output signals sum and carry to analog.It acts as the input for the output analog block. |
| Point to plot labels | I have added plot labels for 3 input voltages from pulses as a, b, and c.
And also added plot labels for the output sum and carry. |
| Click on Generate netlist button on the top toolbar | Next, let us generate the netlist of the circuit.
Click on the Generate Netlist button in the top toolbar. The Netlist window opens up. |
| Click on the Spice option in the Netlist tab | Now, Click on the last option, Spice. |
| Click on the Default format check box and click Generate | Check the Default format box.
|
| Click the Save button on the Save Netlist File window | The Save Netlist File dialog box opens.
We see the netlist file for the full_adder file is generated. Click on the Save button to save the netlist. |
| Click on annotate button in the Annotate Schematic window | A new window named Annotate Schematic opens automatically.
I will now annotate the unannotated components of the circuit. Click on the annotate option at the bottom. |
| Click on OK button in the warning dialogue box | The dialogue box displays the unannotated components that will be annotated.
To proceed with annotation click on OK button |
| Switch to the eSim main window
Click on Convert KiCad to Ngspice |
Let us switch to the eSim main window to simulate the circuit.
Click on Convert KiCad to Ngspice icon in the left toolbar. |
| Click on the Ngspice Model tab | Let us set the simulation parameters of bridges.
Under the kicadToNgspice-1 window, click on the Ngspice Model tab. |
|
set out_low as 0.5 set out_high as 3.3 |
Now, Scroll down to view all the DAC parameters.
Let us add the DAC parameters as shown here. out_low represents the Minimum Output Low Voltage. out_high represents the Maximum Output High Voltage. |
| set in_low as 0.5
set in_high as 3.3 |
Now, scroll down to view all the ADC parameters
Let us add the ADC parameters as shown here. in_low represents the Minimum Input Low Voltage. in_high represents the Maximum Input High Voltage. |
| Only narration | Default values are considered if the user does not fill the remaining parameters.Here we have set the analysis as transient.
In order to set parameters in other tabs, please refer to the previous eSim tutorials. |
| Click on the Convert button | Then, click on the Convert button at the bottom. |
| Click OK on the information dialogue box | A new netlist gets created with the default simulation parameters.
The information dialog box displays that Kicad to Ngspice conversion is done. Click on the OK button. |
| Click on the Simulation icon at the left toolbar | Let us now simulate and check the outputs of the circuit.
|
| Point to the Ngspice Plots | We can see the plots through different windows.
The input plots of a, b, and c are shown here. The output plots of the sum and carry are shown in separate windows. |
| Point to a and b plots | a and b are two 1-bit inputs. |
| Point to c plot | c represents the input carry signal. |
| Point to sum plot | sum shows the addition of a, b, and c bits.We see the sum goes high when any one or all of the a, b, and c are high. |
| Point to carry plot | carry shows the carry generated by the addition of a, b, and c bits.We see the carry goes high when any two or all of the a, b and c are high |
| Point to the full_adder.cir.out window | We see the digital input and output values in the full_adder.cir.out window.
With this, we have successfully simulated the full_adder circuit. |
| Show Slide:
Checks to be done |
Refer to the Appendix of the eSim user manual in this link.
https://static.fossee.in/esim/manuals/eSim_Manual_2.2.pdf It has instructions on writing VHDL models in case of any errors. It also mentions the Checks to be done before Simulation in NGHDL. |
| Show Slide:
NGHDL Simulator |
For details on the NGHDL simulator and its implementation, please refer to this paper: |
| Show Slide:
Microcontroller Simulation |
The Microcontroller Simulations can also be incorporated through NGHDL.
For more details, please visit this site: |
| Show Slide:
Summary |
This brings us to the end of the tutorial. Let us summarize.
In this tutorial, we have
|
| Show Slide:
Assignment |
As an assignment, please do the following:
eSim-2.2/nghdl/Example/combinational-logic.
|
| Show Slide:
About Spoken Tutorial Project |
The video at the following link summarizes the Spoken Tutorial project.
Please download and watch it. |
| Show Slide:
Spoken Tutorial Workshops |
The Spoken Tutorial Project team conducts workshops and gives certificates.
For more details, please write to us. |
| Show Slide:
Answers for THIS Spoken Tutorial |
Please post your timed queries in this forum. |
| Show Slide:
FOSSEE Forum |
For any general or technical questions on eSim, visit the FOSSEE forum and post your question. |
| Show Slide:
Circuit Simulation Project |
The FOSSEE team coordinates the Circuit Simulation Project.
For more details, please visit this site. |
| Show Slide:
Textbook Companion Project |
The FOSSEE team coordinates the TextBook Companion Project.
For more details, please visit this site. |
| Show Slide:
Lab Migration |
The FOSSEE team coordinates the Lab Migration Project.
For more details, please visit this site. |
| Show Slide: Acknowledgements | Spoken Tutorial Project is funded by the Ministry of Education, Government of India. |
| Show Slide:
Thank you |
This is Harisankar a FOSSEE summer fellow 2022, IIT Bombay signing off.
Thanks for joining. |
