Nancyvarkey at 11:58, 11 January 2023

2023-01-11T11:58:47Z

Nirmala Venkat: Created page with " {| border="1" |- || '''Visual Cue''' || '''Narration''' |- || Show Slide:''' Title slide''' || Welcome to the '''Spoken Tutorial''' on '''Advanced NgVeri.''' |- || Sho..."

2023-01-10T06:24:06Z

Created page with " {| border="1" |- || '''Visual Cue''' || '''Narration''' |- || Show Slide:''' Title slide''' || Welcome to the '''Spoken Tutorial''' on '''Advanced NgVeri.''' |- || Sho..."

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{| border="1"
|-
|| '''Visual Cue'''
|| '''Narration'''
|-
|| Show Slide:''' Title slide'''
|| Welcome to the '''Spoken Tutorial''' on '''Advanced NgVeri.'''
|-
|| Show Slide:''' Learning Objectives'''

|| In this tutorial, we will learn how to,
* Add '''dependency files''' and '''folders'''
* Remove '''NgVeri '''models and
* Add and remove '''lint_off '''commands.
in '''Ngveri'''.
|-
|| Show Slide:''' System Requirements'''

|| To record this tutorial, I am using* '''Ubuntu OS v20.04 '''
* '''eSim v2.2'''
The process demonstrated in this tutorial is similar in '''Windows OS''' also.
|-
|| Show Slide:''' '''

'''Prerequisites'''

[https://esim.fossee.in/ https://spoken-tutorial.org]
|| To follow this tutorial, the learner must have:
* Basic knowledge of '''eSim'''
* Familiarity with '''Verilog''' and '''Mixed Signal Simulation'''
* Basic knowledge of '''NgVeri''' feature

For pre-requisite '''eSim''' tutorials, please visit this website.
|-
|| Show Slide:''' Code Files'''

||
* The files used in this tutorial are provided in the '''Code files''' link.
* Please download and extract the files.
* Make a copy and then use them while practicing.

|-
|| Only narration
||First we will see how to add the '''dependency files'''
|-
|| '''Slide:'''

'''Example: Add Dependency Files'''

||
*For demonstration, we have taken the''' 8bit_vedic_multiplierproject.'''
* Note that the '''8bit_vedic_multiplier '''is taken from [https://opencores.org/projects/8bit_vedic_multiplier opencores.org]
* The same project folder is provided in the Code files link.

|-
|| Click on the '''Makerchip''' tab.
|| Go to the '''eSim '''main window and click on the '''Makerchip''' tab.

Now we will see how to add the '''dependency files'''.
|-
|| Click on''' Add Top Level Verilog File'''
|| For this, click on the''' Add Top Level Verilog File''' option.
|-
|| Click on '''Downloads'''>>'''8bit_vedic_multiplier'''

Browse the''' full_adder.v '''file

Click on '''Open'''
|| Go to the '''Downloads''' Folder and locate the '''8bit_vedic_multiplier '''folder.

Then select the''' full_adder.v''' file and click on the '''Open''' button.

The file gets loaded.
|-
|| '''Makerchip-NgVeri:'''

Switch to the '''NgVeri''' Tab

Click on '''Run Verilog to Ngspice Converter'''
|| Let us generate the model of '''full_adder.v '''using '''NgVeri'''.

To do so, click on the '''NgVeri '''Tab.

Then click on '''Run Verilog to Ngspice Converter.'''
|-
|| '''Makerchip-NgVeri:'''

Highlighting the error message in the''' Terminal'''
|| We see a message '''There was an error during model creation''' in the terminal.

Let us scroll up to see why the error occurred.
|-
|| Scroll Up

Highlight another error in the '''Terminal'''
|| We see another message '''Cannot find file containing module: 'half_adder''''.

The message indicates that the '''half_adder''' dependency file is missing in the '''eSim '''interface.

So let us add the dependency file.
|-
|| '''Makerchip-NgVeri:'''

Click on the '''Add Other file''' option
||'''Dependency files''' are the files which are an extension to the '''top module''' file.The '''Add Other file''' option is used to add '''dependency''' files to the '''verilog '''file.

Let us click on it.
|-
|| Point towards the''' '''dialog box
|| We see a dialog box open up.
|-
||

Locate and select '''half_adder.v '''file

Click on '''Open'''

Highlight the message in the '''Terminal'''
|| The''' half_adder.v''' is present in the '''8bit_vedic_multiplier '''folder.

Locate and select the''' verilog''' file '''half_adder.v''' from the '''Downloads''' folder.

Click on the '''Open''' button.

In the '''terminal '''we see''' '''that the dependency file '''half_adder.v '''has been added to '''eSim'''.
|-
|| '''Makerchip-NgVeri:'''

Click on the '''Clear Terminal''' Button

Click on''' Run Verilog to Ngspice Converter'''
|| Let us generate the model again.

Click on the '''Clear Terminal''' Button to clear the terminal.

Now Click on''' Run Verilog to Ngspice Converter.'''
|-
|| '''Makerchip-NgVeri:'''

Highlighting the message on the''' Terminal'''
|| We see the''' Model Created Successfully '''has appeared in the '''terminal'''.

This indicates that the previous error has been rectified.

Now the model can be used to create a '''Mixed-Signal schematic''' in '''eSim'''.Please refer to the earlier tutorials to do the same.
|-
|| Only narration
|| Let's now look at adding a dependency folder.

This is done when a user needs to add more files.
|-
|| Switch to''' Makerchip '''tab

Click on''' Add Top Level Verilog File'''

Click on '''Downloads>>8bit_vedic_multiplier>>vedic8x8.v'''

Click on''' Open'''
|| Let us switch back to the''' Makerchip''' Tab by clicking on it.

Then click on''' Add Top Level Verilog File''' to add the '''vedic8x8.v''' '''verilog''' file..

Go to the '''Downloads''' Folder and then to '''8bit_vedic_multiplier. '''

Select the''' vedic8x8.v''' file and click on the '''Open '''button.
|-
|| '''Makerchip-NgVeri:'''

Switch to the '''NgVeri''' Tab

Click on '''Run Verilog to Ngspice Converter'''
|| Let us generate the model of''' vedic8x8.v.'''

To do so, again click on the '''NgVeri '''Tab.

Then click on '''Run Verilog to Ngspice Converter.'''
|-
|| '''Makerchip-NgVeri:'''Highlighting the error message in the''' Terminal'''

Scroll Up

Highlight another error message ‘'''Cannot find file containing module: 'vedic4x4’''' in the '''Terminal'''
|| We see the same error message in the terminal.

Let us scroll up to see why the error occurred.We see another message '''Cannot find file containing module: 'vedic4x4''''.

It indicates that the ''''vedic4x4' '''and the other''' '''dependency files are missing.

So, we will now add all the files at once using the''' Add Folder''' Option.
|-
|| '''Makerchip-NgVeri:'''

Click on''' Add Folder'''
|| Click on the '''Add Folder '''option.
|-
|| Locate and select the '''8bit_vedic_multiplier '''folder

Click on '''Open'''
|| A dialog box opens.

Locate and select the '''8bit_vedic_multiplier '''folder.

Click on the '''Open '''button.
|-
|| Point to the '''Message '''dialog box
|| A pop-up appears.

If we click on '''Yes, '''the only contents of the folder will be added'''.'''

If we click on '''No, '''the complete folder will be added.
|-
|| '''Makerchip-NgVeri:'''

Click on '''Yes'''

Highlight the message in the '''Terminal'''
|| I will click on '''Yes.'''

We can see in the '''Terminal '''that the '''dependency''' folder has been added.

'''Dependency files'''/'''folders''' help us to divide a large '''verilog''' file into '''submodules'''.

The user can make use of this option depending upon the requirement.
|-
|| '''Makerchip-NgVeri:'''

Click on''' Run Verilog to Ngspice Converter'''
|| Let us generate the model again.

Click on the '''Clear Terminal''' Button to clear the terminal.

Now Click on''' Run Verilog to Ngspice Converter.'''
|-
|| '''Makerchip-NgVeri:'''

Highlighting the message on the''' Terminal'''
|| We see the''' Model Created Successfully '''has appeared in the terminal without any errors.
|-
|| Only Narration
|| Next, let us look at the concept of '''Linting '''in eSim.
|-
|| '''Slide:'''

About '''lint:'''
||
* '''Linting '''helps us to check programmatic or stylistic errors in a program.

* '''lint_off '''errors/warnings create a problem in compilation of '''NgVeri'''.

* To ignore these '''lint_off errors, lint_off''' '''commands '''need to be added or removed.

* To know more about '''lint_off commands''', please refer this website: [https://verilator.org/guide/latest/warnings.html#list-of-warnings https://verilator.org/guide/latest/warnings.html#list-of-warnings]

|-
|| Click on the '''Edit lint_off '''dropdown

|| Let us explore the '''Edit lint_off '''option by clicking on its dropdown.

We see the list of all the '''lint_off '''commands.The''' lint_off''' commands help to ignore''' lint_off warnings''' in '''Verilator '''compilation.
|-
|| Select '''EOFNEWLINE'''
|| Let us remove one of the '''lint_off''' commands and see what happens.

Select '''EOFNEWLINE '''from the dropdown menu.'''EOFNEWLINE '''occurs if there is no empty line at the end of file.
|-
|| Click on '''OK'''
|| Click on '''OK '''in the '''Warning '''dialog box.
|-
|| Click on the '''Edit lint_off''' dropdown
|| Now, again click on '''Edit lint_off '''dropdown.

We see that the command '''EOFNEWLINE '''is removed successfully.
|-
|| '''Makerchip-NgVeri:'''

Click on the '''Clear Terminal''' Button

Click on''' Run Verilog to Ngspice Converter'''
|| Let us generate the model again to see the changes.

Click on the '''Clear Terminal''' Button and then on''' Run Verilog to Ngspice Converter'''
|-
|| '''Makerchip-NgVeri:'''Highlighting the error message in the''' Terminal'''

Scroll Up

Highlight another error in the '''Terminal'''
|| We see a message '''There was an error during model creation''' in the terminal.

Let us again scroll up to see why the error occurred.We see another message '''Missing newline at end of file'''.
|-
|| Point to the the '''text box''' near''' Add Lint_off''' option
|| To resolve this error we need to add the '''EOFNEWLINE''' '''Lint_off''' command again.

We can see a '''text box '''to the left of the '''Add Lint_off '''option.
|-
|| Type '''EOFNEWLINE'''

Click on '''Add Lint_Off'''
|| Type a '''lint_off command''' in the textbox.

Let us type '''EOFNEWLINE''' in the text box.

Then, click on the '''Add Lint_Off '''option.
|-
|| Click on '''Edit lint_off''' dropdown
|| Go back to the '''Edit lint_off '''dropdown and click on it.
|-
|| Point towards '''EOFNEWLINE '''command
|| We see that the command '''EOFNEWLINE '''is now added.
|-
|| '''Makerchip-NgVeri:'''

Click on the '''Clear Terminal'''

Click on''' Run Verilog to Ngspice Converter'''
|| Let us generate the model again.

Click on the '''Clear Terminal''' Button to clear the terminal.

Now Click on''' Run Verilog to Ngspice Converter'''

|-
|| '''Makerchip-NgVeri:'''

Highlighting the message on the''' Terminal'''
|| We see the''' Model Created Successfully '''in the terminal.

|-
|| Point towards '''Edit modlst '''
|| Let us look at how to see all the models present in '''NgVeri''' .

The '''Edit modlst '''option is used to see all the models present in the '''NgVeri.'''

|-
|| Click on the '''Edit modlst '''

|| Click on the '''Edit modlst '''dropdown.

We see a list of models.
|-
|| Only Narration
|| Let us see the purpose of removing the '''NgVeri '''model.
|-
|| '''Slide:'''

'''Removing NgVeri Model:'''
||
* While creating a model, sometimes we might get an error which can’t be resolved.
* The error creates problems in building '''NgVeri''' for future '''verilog''' files also.
* In such a case, the error giving model must be removed by the '''Edit modlst '''option.
* The error model can be identified in the terminal.
* The '''Edit modlst '''option is useful to users to remove redundant models.
* It also reduces memory space

|-
|| Select '''counter4bit'''
|| For example, let us remove the '''counter4bit''' model assuming that it is giving error.

To do so, click on '''counter4bit '''from the dropdown.
|-
|| Click on '''OK'''
|| Click on '''OK '''in the Warning''' '''dialog box.
|-
|| Only Narration
|| The process may take some time.
|-
|| Highlight the build commands
|| We see the build commands have run in the terminal.
|-
||

Click on '''Edit modlst''' dropdown menu
|| Let us now check whether the model is removed.

Again click on the '''Edit modlst '''dropdown.

We see that the model '''counter4bit '''is removed successfully.
|-
|| Show Slide:'''Summary'''

|| This brings us to the end of this tutorial.

Let us summarize.

In this tutorial, we have
* Added '''dependency''' files and folders
* Removed '''NgVeri''' models and
* Added and removed '''lint_off '''commands

in '''NgVeri'''.
|-
|| Show Slide:''' Assignment'''
|| As an assignment, please do the following:* Click on the''' Edit lint_off'''
* Check all the commands in the drop down
* Remove the '''CASEX''' '''lint_off '''command
* Click on the '''Run Verilog to Ngspice Converter''' to generate the model again
* Check if there are errors.
* Add the '''CASEX''' command again using the '''Add lint_off '''option.
* Check whether it has been added by clicking on''' Edit lint_off''' dropdown.

|-
|| Show Slide:''' About the Spoken Tutorial Project'''
|| The video at the following link summarizes the'''Spoken Tutorial''' project.

Please download and watch it.
|-
|| Show Slide: '''Spoken Tutorial Workshops'''
|| The '''Spoken Tutorial''' Project team conducts workshops and gives certificates.

For more details, please write to us.
|-
||Show Slide: '''Answers for THIS Spoken Tutorial'''
|| Please post your timed queries in this forum.
|-
|| Show Slide:''' FOSSEE Forum'''
||For any general or technical questions on '''eSim''', visit the '''FOSSEE''' forum and post your question.
|-
|| Show Slide: '''Circuit Simulation Project'''
||The '''FOSSEE''' team coordinates the '''Circuit Simulation Project.'''

For more details, please visit this site.
|-
|| Show Slide: '''Textbook Companion Project'''
||The '''FOSSEE''' team coordinates the '''TextBook Companion Project.'''

For more details, please visit this site.
|-
|| Show Slide: '''Lab Migration'''

||The '''FOSSEE''' team coordinates the '''Lab Migration Project.'''

For more details, please visit this site.
|-
|| Show Slide:

'''Acknowledgement'''
||The '''Spoken Tutorial''' project is funded by the '''Ministry of Education''', '''Government of India. '''
|-
|| Show Slide: '''Thank you '''

|| This is '''Josiga''', a''' FOSSEE summer fellow 2022, IIT Bombay''' signing off.
Thanks for joining.
|-
|}

ESim/C4/Advanced-NgVeri/English - Revision history

Nancyvarkey at 11:58, 11 January 2023

Nirmala Venkat: Created page with " {| border="1" |- || '''Visual Cue''' || '''Narration''' |- || Show Slide:''' Title slide''' || Welcome to the '''Spoken Tutorial''' on '''Advanced NgVeri.''' |- || Sho..."